https://salti.tech/tags/digdesign/ Recent content in Digital Design on Salti Hugo -- gohugo.io en Mon, 10 Mar 2025 16:37:22 -0500 https://salti.tech/posts/aes_accelerator/ Fri, 12 Jun 2026 23:24:17 -0500 https://salti.tech/posts/aes_accelerator/ Designed an AES Accelerator on FPGA for CPRE 4880 Embedded Systems Design. Github Project Background Advanced Encryption Standard (AES) is a symmetric encryption algorithm. AES is also more of a group; there is AES-128, AES-192, and AES-256 —where the number refers to the size of the blocks in bits. There are different ways AES can be used to provide security, but the most primitive usage of AES is AES-ECB (electronic codebook) where blocks of input are encrypted or decrypted independently with a key. https://salti.tech/posts/larng/ Mon, 10 Mar 2025 18:06:52 -0500 https://salti.tech/posts/larng/ Low Latency True Random Number Generator. GitHub Page Status: In Fabrication Stage When I was taking 281 Digital Logic my first semester, I remember being tought about latches. Seeing the diagram of a latch, and seeing the truth table, I wasn’t able to trace the initial value. This got me curious. I knew that when you power the circuit up, it has to take on some value. It seemed to me that this value might be random. https://salti.tech/posts/mips_32_processor/ Mon, 10 Mar 2025 16:34:10 -0500 https://salti.tech/posts/mips_32_processor/